1. Field of the Invention
The present invention relates to a pulse width modulation method, and particularly relates to a method for pulse-width modulating (PWM) a digital signal input from a digital signal output unit in a digital-analogue (D/A) converter. Also, the present invention relates to a D/A converter using this pulse width modulation method.
2. Description of the Related Art
In a process of converting a digital signal to an analogue signal (digital-analogue (D/A conversion)), a pulse width modulation (PWM) is widely used.
In a well-known PWM method, based on the digital signal inputted to a PWM modulator in each PWM cycle, a time width of a section of a high level (H level) of a pulse (PWM signal) and a time width of a section of a low level (L level) of the pulse (PWM signal) are determined, and a profile of an output pulse is determined.
FIG. 1 is a diagram exemplifying the PWM signal formed in one system of a well-known PWM system. In this example, a point where the pulse changes from the section of the L level to the section of the H level (Hereinafter, this point is referred to as a “rising” of a PWM signal.) is fixed with respect to a PWM timing signal, and the point where the PWM signal changes from the section of the H level to the section of the L level (Hereinafter, this point is referred to as the “falling” of the PWM signal.) is determined so as to correspond to the time width of sections of the H level and the L level determined based on the inputted digital signal, thereby determining the profile of the pulse (PWM signal).
PWM cycles P1 and P2 shown in FIG. 1 are defined by the PWM timing signal, and a PWM clock shown in FIG. 1 is a clock signal for dividing a PWM cycle T into 16. In this figure, a cycle of this PWM clock is shown by t. Rising and falling of an output pulse (PWM signal) are realized based on the PWM clock. Therefore, if the use of the PWM signal with the entire section within 1 PWM cycle being set at H level or L level is allowed, profiles of the PWM signal which can be realized within one cycle of the PWM cycles are as much as 17 kinds. This means that the digital signal having the gradation number of 17 steps is PWM modulatable. When the digital signal inputted in the PWM modulator is correlated to an integer value of equal numbers of plus or minus centering around zero, 17 kinds such as −8, −7, −6, −5, −4, −3, −2, −1, 0, +1, +2, +3, +4, +5, +6, +7, and +8 are possible as values shown by the inputted digital signal. That is, the integers of not less than −8 and not more than +8 can be set as the values in a value range shown by the inputted digital signal.
However, when there is a limit in a response speed of a device using the PWM signal (pulse) outputted from the PWM modulator, a minimum width of each section width of the H level and the L level of the PWM signal is limited to an extent allowing this device to respond (for example, limited to 2t or more), and a stable operation of this device is secured. In addition, in some cases, the PWM signal is formed so as to include rising and falling, so that an area formed by the pulse included in the profile is linearly increased or decreased corresponding to a change of the profile of the PWM signal.
As described above, when the minimum widths of the section widths of the H level and the L level are limited to 2PWM clock (2t) or more so as to secure the stable operation of the device positioned on a lower stream side or when the rising and falling is surely provided within one cycle of the PWM cycles by limiting the minimum width of the section width of the H level and the L level to 2PWM clock (2t) or more, the gradation number of the PWM modulatable digital signal is decreased.
In an example of FIG. 1, the minimum value of the section width of the H level and the L level is set at 4PWM clock (4t), respectively. A PWM signal S101 is a pulse having a maximum H level section width (minimum L level section width) under the aforementioned limit. A PWM signal S103 shows an example of the PWM signal realized by advancing the timing of falling than that of the PWM signal S101. A PWM signal S105 is an outputted PWM signal when the timing of falling is maximally advanced under the aforementioned limit. The PWM signal S105 has an H level section width (maximum L level section width) under the aforementioned limit. Thus, under the aforementioned limit, the PWM signal having 9 kinds of profiles can be outputted, and the digital signal having the gradation number of 9 steps at maximum is PWM modulatable. That is, the integers of not less than −4 and not more than +4 can be set as the values in the value range shown by the digital signal input.
Japanese Examined Patent Application Publication No. 07-087375 (JP 07-087375 B) discloses pulse width modulation (PWM) in a delta-sigma (ΔΣ) type digital-analogue (D/A) converter. Also, “Designing and manufacturing of Class D/digital amplifier”, written by Jun Honda, CQ Publishing, discloses PWM to a digital signal, in FIG. 9 or FIG. 30 of section 9-7 (page 214) of chapter 9. In JP 07-087375 B and “Designing and manufacturing of Class D/digital amplifier”, as shown in FIG. 2, the PWM signal is outputted so that a center of the pulse of the PWM signal is coincident to a center point on the time axis of each PWM cycle.
In the example of FIG. 2 also, like the example of FIG. 1, each section width of the H level and the L level has at least a section width of 4t or more, and a continuance of sections of the H level or the sections of the L level is prohibited. In this case, both ends of one PWM cycle form an L level section having at least a section width of 2t or more, as shown in a PWM signal S107. Accordingly, in each PWM cycle P1 and P2, the PWM signal with the section width of the H level having a section width of not less than 4t and not more than 12t can be outputted as shown in a PWM signal S109 or S111. This means that the digital signal having the gradation number of 5 steps at maximum is PWM modulatable.
In the example of FIG. 2, a boundary part of the PWM cycle is always the section of the L level. However, of course, if it is designed so that the H level and the L level are replaced and used, the PWM signal can be outputted, with the boundary part of the PWM cycle set to be always H level.
Thus, in the present PWM method, in order to overcome the problem regarding the response speed of the device using the PWM signal and the problem such as a linearity deterioration caused by increase/decrease of the area of the pulse, the gradation number of the digital signal that can be inputted is significantly reduced.